Identifying and processing essential and non-essential code separately
US7437542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.