Method and system for updating a value of a slow register to a value of a fast register
US7437587B2 · kind B2 · utility
2Cited by
5References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to synchronizing registers. An embodiment includes a plurality of processing cells each includes a plurality of CPUs, which run at different frequencies and each of which has an ar.itc timer register. A CPU in the fastest cell of the plurality of cells is referred to as the fast CPU. CPUs in slower cells are referred to as slow CPUs. At predetermined time intervals, slow CPUs are provided with the ar.itc value of the fast CPU to replace the values of their ar.itc. As a result, values in the ar.itc registers are synchronized without providing negative time. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.