Method and apparatus for hardware timing optimizer
US7437591B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Oct 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.