Test pattern generating method and apparatus and storing medium for storing test pattern generating program
US7437646B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jul 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is a test pattern generating method. And the test pattern generating method provides a counting step for counting the number of faults becoming undetectable respectively, at each of states 0 and 1 that are able to be given to each of input pins of EOR gates when each of the EOR gates becomes a D frontier (different frontier) or a J frontier (justify frontier), a selecting step for selecting a state in which the number of faults becoming undetectable is smaller in the 0 and 1 states as an allocating state to the input pin, based on a counted result at the counting step, and step for generating the test pattern based on a selected state at the selecting step. With this, dynamic compaction can be effectively executed by restraining the increase of the number of test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.