Pre-emptive interleaver address generator for turbo decoders
US7437650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Apr 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6519
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.