Method for manufacturing semiconductor memory
US7439126B2 · kind B2 · utility
1Cited by
5References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diameter portion by etching an insulating film formed on the large-diameter portion using the large-diameter portion as an etching stopper layer, and a step of forming a conductive film inside the hole so as to serve as an electrode for the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.