Method for producing tiered gate structure devices
US7439166B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | May 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.