Fast bias for power amplifier gating in a TDMA application
US7439810B2 · kind B2 · utility
12Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Sep 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
RF amplifier bias system for TDMA application. A bias circuit (200) is coupled to an RF power amplifier (201) circuit. The bias circuit includes a charge pump/sink circuit (215) a voltage reference circuit (204) and voltage scaling circuit (208, 210, 214). The bias system provides fast response time when transitioning between various bias voltage applied to an FET RF transistor (244).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.