Power-state management of peripheral device by north bridge for power management of computer system
US7441128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Dec 20, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.