Skew adjusting circuit and method for parallel signals
US7441139B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Feb 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The skew adjusting circuit for parallel signals includes: a deskew signal generating circuit which generates a deskew signal by performing a predetermined logical operation and transmits the deskew signal to a receiving circuit; a skew detecting circuit which detects the skew by obtaining correlation between the deskew signal and the data signal and then obtaining an average value of the correlation; and a delay amount adjusting circuit which adjusts the skew by controlling the amount of delay of the data signal in accordance with the average value obtained by the skew detecting circuit. As a result, it is possible to reduce power consumption and circuit size, while suppressing the number of logic processing circuits to be added for skew adjustment, when parallel signals are transmitted in circuits which needs high-speed characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.