Low complexity decoding of low density parity check codes
US7441178B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Apr 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1108
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.