Package having bond-sealed underbump
US7443017B2 · kind B2 · utility
3Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2006 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jan 16, 2027 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00269
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A package for containing microelectromechanical devices includes a first substrate wafer, and a second substrate wafer made of an optical quality material. An underbump is interposed between the first and second substrate wafers. The underbump is composed of a standoff region and a localized bond region. The first and second substrate wafers and the underbump define a chamber that contains at least one microelectronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.