Differential output circuit with stable duty
US7443207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Aug 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through the bias circuit, and gates of the first and second MOS transistors receive a differential input signal. Third and fourth MOS transistors of a second conductive type are connected with the first and second MOS transistors through first and second resistance elements, respectively, and connected with a second voltage. A first connection node between the first MOS transistor and the first resistance element is connected with a gate of the fourth MOS transistor, and a second connection node between the second MOS transistor and the second resistance element is connected with a gate of the third MOS transistor. A differential output signal is outputted from a first output node between the first resistance element and the third MOS transistor and a second output node between the second resistance element and the fourth MOS transistor in response to the differential input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.