CDMA power amplifier design for low and high power modes
US7443236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2007 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/75
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.