Semiconductor memory device and method of testing the same
US7443748B2 · kind B2 · utility
3Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept LOW during a precharge period, and activation/deactivation of the two equalizing elements is separately controlled. A failure such as a defect in one of the two equalizing elements subjected to the on/off control by the control signal can be thereby detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.