Deadlock avoidance queuing mechanism
US7443869B2 · kind B2 · utility
22Cited by
10References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/56
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.