Circuitry for padded communication protocols
US7443922B1 · kind B1 · utility
6Cited by
1References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2003 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Aug 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0064
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.