Adjustable segmented power amplifier
US7444124B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Aug 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture, circuits, systems and a method for amplifying an analog signal. The architecture and/or circuit generally includes a first fixed stage (e.g., a predriver) and an adjustable stage. The first fixed stage may be configured to amplify an analog signal and provide a first amplified analog output at a first common node. The adjustable stage may comprise a plurality of independently selectable parallel amplifier segments. Each of the parallel segments may have an input at the first common node and an output at a second common node, a transistor having a control terminal, and a first inductor in electrical communication with the control terminal of the transistor. The adjustable stage may be configured to apply a bias to the control terminal of the transistor in a selected segment and to provide an output signal in one of a plurality of a power ranges corresponding to a number of selected parallel amplifier segments. The output signal generally has a minimum power efficiency when two or more of the parallel segments are selected. The present invention advantageously provides a relatively compact power amplifier with an extended output power range at which the amplifier is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.