Global interrupt and barrier networks
US7444385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2002 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network include…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.