Retrieving data blocks with reduced linear addresses
US7444457B2 · kind B2 · utility
1Cited by
1References
26Claims
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Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Apr 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.