Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress
US7444490B2 · kind B2 · utility
11Cited by
5References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 9, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Mar 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.