Address translation for input/output devices using hierarchical translation tables
US7444493B2 · kind B2 · utility
44Cited by
8References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jan 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.