System and method for circuit noise analysis
US7444600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jul 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract file for one or more blocks of a circuit. These abstract files may include noise tolerances for input pins and bi-directional pins of a block, along with noise tolerances for those output pins of the block which also feed to an input of one or more gates internal to the block. Using these noise abstracts a unit of the circuit may be analyzed, or the circuit itself may be analyzed for possible noise induced failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.