Fabrication process of memory cell
US7445972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2007 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Dec 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.