Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
US7446033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jan 23, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24207
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.