Display panel
US7446338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Dec 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/233
Abstract
A display panel includes a transistor array substrate which has a plurality of pixels and is formed by providing a plurality of transistors for each pixel, each of the transistor having a gate, a gate insulating film, a source, and a drain. A plurality of interconnections are formed to project to a surface of the transistor array substrate and arrayed in parallel to each other. A plurality of pixel electrodes are provided for each pixel and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections. Each of a plurality of light-emitting layers is formed on each pixel electrode. A counter electrode is stacked on the light-emitting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.