Module
US7447038B2 · kind B2 · utility
5Cited by
12References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10545
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.