Semiconductor integrated circuit
US7447059B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jun 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit having an internal SRAM that includes a plurality of arrayed memory cells, including a first bit line and a second bit line that are connected to first ports and a third bit line and a fourth bit line that are connected to second ports of the memory cells, a first and second transistor respectively compose first ports of adjacent first and second memory cells and having shared impurity diffusion region connected to the first bit line via a first interconnection, a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection a fourth and fifth transistor respectively composing the first ports of the first and second memory ceils and having a shared impurity diffusion region connected to the second bit line via a third interconnection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.