System and method for providing a CMOS compatible single poly EEPROM with an NMOS program transistor
US7447064B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | May 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.