Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
US7447289B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jun 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.