Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files
US7447812B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.