Multi-table branch prediction circuit for predicting a branch's target address based on the branch's delay slot instruction address
US7447884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jun 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched from an output of the first storage unit. When the first detector detects previous branching of the instruction of the present address, the second storage unit stores the branched address corresponding to the address of the instruction to be executed following the branching instruction. When a second detector detects an output of a program counter as the address of the instruction to be executed following the branching instruction, the second storage unit outputs the branched address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.