ECC coding for high speed implementation
US7447948B2 · kind B2 · utility
37Cited by
15References
18Claims
0Family size
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Key dates
| Filing date | Nov 21, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jan 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.