Memory device and memory error correction method
US7447950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2004 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Apr 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.