Dynamic soft-error-rate discrimination via in-situ self-sensing coupled with parity-space detection
US7447957B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jan 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system that facilitates distinguishing between soft errors and the onset of hardware degradation in a computer system. During operation, the system receives notifications of correctable-error events from a plurality of memory components. The system then averages numbers of correctable-error events from the plurality of memory components to generate an average number of correctable-error events across the plurality of memory components. The system subtracts the number of correctable-error events for a given memory component in a given time interval from the average number of correctable-error events to generate a residual number of correctable-error events for the given memory component in the given time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.