Inversion of scan clock for scan cells
US7447961B2 · kind B2 · utility
19Cited by
17References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jun 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A scan clock source, coupled to the scan chain, generates a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells. The first and the second clock signals have an inverted relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.