Offset test pattern apparatus and method
US7447965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/244
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.