Error detection and correction in data transmission packets
US7447980B2 · kind B2 · utility
11Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/154
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method of using recursive cyclic redundancy check (CRC)+forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder+FEC to achieve better coding gain. The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme for implementing the recursive CRC/RS+FEC in very large scale integrated circuit chip (VLSI) hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.