Signal flow driven circuit analysis and partitioning technique
US7448003B2 · kind B2 · utility
5Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Aug 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.