Method, system, and program product for automated verification of gating logic using formal verification
US7448008B2 · kind B2 · utility
5Cited by
11References
17Claims
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Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Feb 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.