Nonlinear via arrays for resistors to reduce systematic circuit offsets
US7449783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | May 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A thin film resistor structure includes a plurality of thin film resistor sections. Conductive vias (5) are disposed on a first end of each of the thin film resistor sections, respectively. The first conductor (2) is connected to the vias of the first end, and a second conductor (3) is connected to vias on a second end of each of the thin film resistor sections. A distribution of a parameter of a batch of circuits including the thin film resistor structure indicates a systematic error in resistance values. Based on analysis of the distribution and the circuit, or more of the vias are individually moved at the layout grid level by a layout grid address unit to reduce the systematic error by making corresponding adjustments on a via reticle of a mask set used for making the circuits. Expensive laser trimming of thin film resistors of the circuit is thereby avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.