Reading circuit and method for a nonvolatile memory device
US7450428B2 · kind B2 · utility
2Cited by
7References
29Claims
0Family size
Inventors
Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jun 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.