Memory system, a memory device, a memory controller and method thereof
US7450441B2 · kind B2 · utility
6Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jun 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.