Method to identify or screen VMIN drift on memory cells during burn-in or operation
US7450452B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2007 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.