Low power dual processor architecture for multi mode devices
US7450963B2 · kind B2 · utility
20Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.