Method and system for onboard bit error rate (BER) estimation in a port bypass controller
US7451362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Dec 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the method may comprise receiving via a first port of the port bypass controller, a data stream comprising at least one known bit pattern. Upon locking onto at least a portion of the known bit pattern in the received data stream, a bit error rate may be generated based on a bit-by-bit comparison of at least a portion of the data stream received after locking occurs. At least a portion of the data stream may be compared with a corresponding portion of expected data. The bit error rate may be calculated based on results from comparing at least a portion of the data stream with a corresponding portion of the expected data. The known bit pattern may be internally generated within the port bypass controller or it may be externally generated by a host system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.