Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories

US7452776B1 · kind B1 · utility

Assignee

• ProMOS Technologies PTE. Ltd. · SG

Inventors

• Yue-Song He · San Jose, US
• Len Mei · Hsinchu, TW

Key dates

• Filing date: Apr 24, 2007
• Grant date: Nov 18, 2008
• Expiry date: Apr 24, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6213

Abstract

A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and t…