Method of forming a stable transistor by dual source/drain implantation
US7452780B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor includes: forming a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming low-energy ion implantation regions in the silicon substrate and in alignment with both sidewalls of the gate polysilicon layer; forming gate spacers on both sidewalls of the gate polysilicon layer; forming amorphous layers on surfaces of the gate polysilicon layer and the silicon substrate by implanting impurities at a low implantation energy into the gate polysilicon layer and the silicon substrate; and forming high-energy ion implantation regions by implanting source/drain impurities at a high implantation energy into the silicon substrate including the gate polysilicon layer and the amorphous layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.