Non-volatile semiconductor memory device
US7453117B2 · kind B2 · utility
4Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jun 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.