Clock translator and parallel to serial converter
US7453288B2 · kind B2 · utility
0Cited by
35References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.